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Espressif Systems /ESP32-S2 /I2S0 /PD_CONF

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Interpret as PD_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FIFO_FORCE_PD)FIFO_FORCE_PD 0 (FIFO_FORCE_PU)FIFO_FORCE_PU 0 (PLC_MEM_FORCE_PD)PLC_MEM_FORCE_PD 0 (PLC_MEM_FORCE_PU)PLC_MEM_FORCE_PU 0 (DMA_RAM_FORCE_PD)DMA_RAM_FORCE_PD 0 (DMA_RAM_FORCE_PU)DMA_RAM_FORCE_PU 0 (DMA_RAM_CLK_FO)DMA_RAM_CLK_FO

Description

I2S power-down configuration register

Fields

FIFO_FORCE_PD

Force FIFO power-down.
FIFO_FORCE_PU

Force FIFO power-up.
PLC_MEM_FORCE_PD

Force I2S memory power-down.
PLC_MEM_FORCE_PU

Force I2S memory power-up.
DMA_RAM_FORCE_PD

Force DMA FIFO power-down.
DMA_RAM_FORCE_PU

Force DMA FIFO power-up.
DMA_RAM_CLK_FO

Set this bit to force on DMA RAM clock.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd